Recently, the progress of semiconductor technology has driven the integrated circuits technologies toward Ultra Large Scale Integration (ULSI). In ULSI, some negative effects result from the higher integration of devices and the smaller scale of devices. Following the example of MOSFETS, the sheet resistance between the source and drain will increase when the integration of devices is high. It is adverse for high speed operation of MOSFETS. Moreover, the "short channel effect" will occur when the scale of devices is small.
So, the self-aligned silicide (SALICIDE) technology is widely use to increase the packing density of ULSI circuits and to reduce the interconnect for high speed operation. One of some articles relates to the self-aligned silicide (SALICIDE) technology. Please see "A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM, 1996, IEEE, IEDM 96-451". The above article found that Ti-5% W salicide has high-thermal stability up to 800.degree. C. as well as sheet resistance for 0.18 .mu.m devices. However, the SALICIDE process will result in a higher junction leakage due to the metal penetration into Si substrate to spike the junction and/or the residual metal or silicide across the lightly doped drain (LDD) spacer causing a bridge effect between the adjacent devices. One of some articles relates to the above problems. Please see "Process Limitation and Device Design Tradeoffs of Self-Aligned TiSi.sub.2 Junction Formation in Submicrometer CMOS Devices, IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL.38. NO.2. FEBRUARY. 1991".
As for "short channel effect", it could be improved by using the extended ultra-shallow source/drain junction. One of some articles relates to the above problems. Please see "A 0.05 .mu.m-CMOS with Ultra Shallow Source/Drain Junctions Fabricated by 5 Kev Ion Implantation and Rapid Thermal Annealing, 1994, IEEE, IEDM 94-485".
So, solving above problems is required.